Design of modern semiconductors or other electronic devices is extremely complex. A business' success depends on implementing an electronic design process which produces functionally correct hardware efficiently and at the lowest cost. Such a design process depends on design verification techniques capable of determining whether the function of a proposed circuit design conforms to a specification, and extensive analysis and verification methods are required to ensure compliance. A circuit's ability to successfully meet a specification ensures the proper operation of both the circuit in question and the system as a whole. In order to perform such verification, various simulation and other verification tools are used.
Traditional verification methods are based on test benches. Test benches are a verification technique that functions by applying sequences of known test vectors to the circuit inputs and monitoring the results at the circuit outputs. If the expected output values are discovered, the circuit is thought to function properly. However, the test bench approach, along with many currently implemented verification techniques, has become less efficient at finding design errors, both because of increased test duration and other difficulties inherent in verifying complex modern circuit designs. Further, current methods do not scale to large electronic systems comprising perhaps hundreds of millions of devices. Since the detailed evaluation of circuits—especially large circuits—using hand generated test vectors is too difficult and time consuming to be viable, circuit designers have employed other approaches to verification that maximize coverage.
One such technique involves the use of assertions. Assertions provide a very effective means for detecting and localizing design errors, as well as a means for detecting unexercised design areas. At least one type of assertion is a statement about the behavior of the design that, if false, indicates an error in the design. Assertions are usually written by the designer or by verification personnel, however, the writing and implementation of assertions require skills that are not always easy to acquire and apply. Some barriers that can discourage designers from effectively writing assertions for their design include lack of interest in learning about the effectiveness of assertions, a lack of knowledge of an assertion language, a different conceptual view of the design, and tight deadlines.
Assertions can be used with pseudo-random test vectors to help verify a circuit. The pseudo-random test vectors are sometimes constrained by assertions, in which case these assertions are referred to as constraints or assumptions. These constraints or assumptions form a large element of constrained random verification, a technique used to gauge the functionality of complex modern circuit arrangements. As before, this verification approach is based on a test bench. The test bench generates a random (or pseudo-random) set of test vectors, which can represent a much wider range of values than possible using the fixed sequences previously employed. However, arbitrary, random values may not properly stimulate a design in situ. Thus, the random values are constrained to encapsulate the context of the system or subsystem being tested. The test vectors can then be used to stimulate the circuit during simulation and the outputs can be tested against the assertions to verify proper operation of the circuit. These assumptions can often be used in formal verification model checking and elsewhere.